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CY7C132, CY7C136 CY7C136A, CY7C142, CY7C146
2K x 8 Dual-Port Static RAM
Features

Functional Description
The CY7C132, CY7C136, CY7C136A, CY7C142, and CY7C146 are high speed CMOS 2K x 8 dual-port static RAMs. Two ports are provided to permit independent access to any location in memory. The CY7C132, CY7C136, and CY7C136A can be used as either a standalone 8-bit dual-port static RAM or as a MASTER dual-port RAM, in conjunction with the CY7C142/CY7C146 SLAVE dual-port device. They are used in systems that require 16-bit or greater word widths. This is the solution to applications that require shared or buffered data, such as cache memory for DSP, bit-slice, or multiprocessor designs. Each port has independent control pins; chip enable (CE), write enable (R/W), and output enable (OE). BUSY flags are provided on each port. In addition, an interrupt flag (INT) is provided on each port of the 52-pin PLCC version. BUSY signals that the port is trying to access the same location currently being accessed by the other port. On the PLCC version, INT is an interrupt flag indicating that data is placed in an unique location (7FF for the left port and 7FE for the right port). An automatic power down feature is controlled independently on each port by the chip enable (CE) pins.
True dual-ported memory cells that enable simultaneous reads of the same memory location 2K x 8 organization 0.65 micron CMOS for optimum speed and power High speed access: 15 ns Low operating power: ICC = 110 mA (maximum) Fully asynchronous operation Automatic power down Master CY7C132/CY7C136/CY7C136A[1] easily expands data bus width to 16 or more bits using slave CY7C142/CY7C146 BUSY output flag on CY7C132/CY7C136/CY7C136A; BUSY input on CY7C142/CY7C146 INT flag for port to port communication (52-Pin PLCC/PQFP versions) CY7C136, CY7C136A, and CY7C146 available in 52-pin PLCC and 52-pin PQFP packages Pb-free packages available

Logic Block Diagram
R/WL CEL OEL R/WR CER OER
I/O7L I/O0L BUSYL
I/O CONTROL
I/O CONTROL
I/O7R I/O0R BUSYR
[2]
MEMORY ARRAY
[2]
A 10L A 0L
ADDRESS DECODER
ADDRESS DECODER
A 10R A 0R
CEL OEL R/WL INTL[3]
ARBITRATION LOGIC (7C132/7C136 ONLY) AND INTERRUPTLOGIC (7C136/7C146 ONLY)
CER OER R/WR INTR
[3]
Notes 1. CY7C136 and CY7C136A are functionally identical. 2. CY7C132/CY7C136/CY7C136A (Master): BUSY is open drain output and requires pull up resistor. CY7C142/CY7C146 (Slave): BUSY is input. 3. Open drain outputs; pull up resistor required.
Cypress Semiconductor Corporation Document #: 38-06031 Rev. *E
*
198 Champion Court
*
San Jose, CA 95134-1709 * 408-943-2600 Revised March 24, 2009
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CY7C132, CY7C136 CY7C136A, CY7C142, CY7C146
Pinouts
Figure 1. 52-Pin PLCC (Top View) Figure 2. 52-Pin PQFP (Top View)
BUSY R INTR A10R INT L BUSYL R/W L CEL VCC A0L OEL A 10L CER R/W R
A1L A2L A3L A4L A5L A6L A7L A8L A9L I/O0L I/O1L I/O2L I/O3L
8 9 10 11 12 13 14 15 16 17 18 19 20
7 6 5 4 3 2 1 52 51 50 49 48 47 46 45 44 43 42 41 7C136/7C136A 40 7C146 39 38 37 36 35 34 2122 23 24 25 26 27 28 29 30 31 32 33 I/O0R I/O1R I/O2R I/O3R I/O4R I/O5R I/O6R I/O4L I/O5L I/O6L I/O7L NC GND
BUSY R INTR A10R
BUSYL R/W L CEL VCC
A0L OEL A 10L INT L
CER R/W R
52 51 50 49 48 47 46 45 44 43 42 41 40 OER A0R A1R A2R A3R A4R A5R A6R A7R A8R A9R NC I/O7R A1L A2L A3L A4L A5L A6L A7L A8L A9L I/O0L I/O1L I/O2L I/O3L 1 2 3 4 5 6 7 8 9 10 11 12 13 39 38 37 36 35 34 33 32 31 30 29 28 27 OER A0R A1R A2R A3R A4R A5R A6R A7R A8R A9R NC I/O7R
7C136/7C136A 7C146
1415 16 17 18 19 20 21 22 23 24 25 26
NC GND I/O0R I/O1R
I/O2R I/O3R I/O4R
Selection Guide
Specification 7C136-15[4] 7C146-15 15 190 75 7C132-25 [4] 7C136-25 7C142-25 7C146-25 25 170 65 7C132-30 7C136-30 7C142-30 7C146-30 30 170 65 7C132-35 7C136-35 7C142-35 7C146-35 35 120 45 7C132-45 7C136-45 7C142-45 7C146-45 45 120 45 7C132-55 7C136-55 7C136A-55 7C142-55 7C146-55 55 110 35 Unit
I/O5R I/O6R
I/O4L I/O5L
I/O6L I/O7L
Maximum Access Time Maximum Operating Current Com'l/Ind Maximum Standby Current Com'l/Ind
Shaded areas contain preliminary information.
ns mA mA
Note: 4. 15 ns and 25 ns version available in PQFP and PLCC packages only.
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CY7C132, CY7C136 CY7C136A, CY7C142, CY7C146
Maximum Ratings
Exceeding maximum ratings may impair the useful life of the device. These user guidelines are not tested. Storage Temperature ..................................... -65C to +150C Ambient Temperature with Power Applied.................................................. -55C to +125C Supply Voltage to Ground Potential (Pin 48 to Pin 24).................................................-0.5V to +7.0V DC Voltage Applied to Outputs in High Z State .....................................................-0.5V to +7.0V DC Input Voltage ................................................. -3.5V to +7.0V Output Current into Outputs (LOW)............................. 20 mA Static Discharge Voltage.......................................... > 2001V (per MIL-STD-883, Method 3015) Latch up Current.................................................... > 200 mA
Operating Range
Range Commercial Industrial Ambient Temperature 0C to +70C -40C to +85C VCC 5V 10% 5V 10%
Electrical Characteristics
Over the Operating Range
7C136-15[4] 7C146-15 7C132-30[4] 7C136-25, 30 7C142-30 7C146-25, 30 7C132-35,45 7C136-35,45 7C142-35,45 7C146-35,45 7C132-55 7C136-55 7C136A-55 7C142-55 7C146-55
Parameter
Description
Test Conditions
Unit
Min VOH VOL VIH VIL IIX IOZ IOS ICC ISB1 Output HIGH voltage Output LOW voltage Input HIGH voltage Input LOW voltage Input load current GND < VI < VCC Output leakage current Output short circuit current[6] VCC Operating Supply Current GND < VO < VCC, Output Disabled VCC = Max., VOUT = GND CE = VIL, Outputs Open, f = fMAX[7] Com'l/ Ind'l Com'l/ Ind'l Com'l/ Ind'l -5 -5 VCC = Min., IOH = -4.0 mA IOL = 4.0 mA IOL = 16.0 mA[5] 2.2 2.4
Max
Min 2.4
Max
Min 2.4
Max
Min 2.4
Max V 0.4 0.5 V V 0.8 V A A mA mA mA
0.4 0.5 2.2 0.8 +5 +5 -350 190 75 -5 -5
0.4 0.5 2.2 0.8 +5 +5 -350 170 65 -5 -5
0.4 0.5 2.2 0.8 +5 +5 -350 120 45 -5 -5
+5 +5 -350 110 35
Standby current CEL and CER > VIH, [7] both ports, TTL f = f MAX Inputs Standby Current CEL or CER > VIH, One Port, Active Port Outputs Open, TTL Inputs f = fMAX[7]
ISB2
135
115
90
75
mA
ISB3
Com'l/ Standby Current Both Ports CEL and Both Ports, CER > VCC - 0.2V, VIN > VCC - 0.2V Ind'l CMOS Inputs or VIN < 0.2V, f = 0 Standby Current One Port CEL or CER > VCC - 0.2V, Com'l/ One Port, Ind'l VIN > VCC - 0.2V or VIN < 0.2V, CMOS Inputs [7] Active Port Outputs Open, f = fMAX
15
15
15
15
mA
ISB4
125
105
85
70
mA
Shaded areas contain preliminary information. Notes 5. BUSY and INT pins only. 6. Duration of the short circuit should not exceed 30 seconds. 7. At f = fMAX, address and data inputs are cycling at the maximum frequency of read cycle of 1/trc and using AC Test Waveforms input levels of GND to 3V.
Document #: 38-06031 Rev. *E
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CY7C132, CY7C136 CY7C136A, CY7C142, CY7C146
Capacitance
This parameter is guaranteed but not tested. Parameter CIN COUT Description Input Capacitance Output Capacitance Figure 3. AC Test Loads and Waveforms
5V OUTPUT 30 pF INCLUDING JIG AND SCOPE Equivalent to: R2 347 R1 893 5V OUTPUT 5 pF INCLUDING JIG AND SCOPE R2 347 BUSY OR INT R1 893 5V 281
Test Conditions TA = 25C, f = 1 MHz, VCC = 5.0V
Max 15 10
Unit pF pF
30 pF
(a)
THEVENIN EQUIVALENT
(b)
3.0V
BUSY Output Load (CY7C132/CY7C136 Only)
ALL INPUT PULSES 10% 90% 90% 10% < 5 ns
250 OUTPUT 1.4V GND
< 5 ns
Switching Characteristics
Over the Operating Range (Speeds -15, -25, -30) [8] 7C136-15 [4] 7C146-15 Min Read Cycle tRC tAA tOHA tACE tDOE tLZOE tHZOE tLZCE tHZCE tPU tPD Read Cycle Time Address to Data Valid
[9]
Parameter
Description
7C132-25 [4] 7C136-25 7C142-25 7C146-25 Min 25 Max
7C132-30 7C136-30 7C142-30 7C146-30 Min 30 Max
Unit
Max
15 15 0 15 10 3 10 3 10 0
[7]
ns 30 ns ns 30 20 ns ns ns 15 ns ns 15 ns ns 25 ns
25 0 25 15 3 15 5 15 0 0 25 5 3 0
Data Hold from Address Change CE LOW to Data Valid [9] OE LOW to Data Valid [9] OE LOW to Low Z [7, 10] OE HIGH to High Z CE LOW to Low Z
[7, 10, 11] [7, 10]
CE HIGH to High Z [7, 10, 11] CE LOW to Power Up [7] CE HIGH to Power Down
15
Shaded areas contain preliminary information. Notes 8. Test conditions assume signal transition times of 5 ns or less, timing reference levels of 1.5V, input pulse levels of 0 to 3.0V and output loading of the specified IOL/IOH, and 30 pF load capacitance. 9. AC test conditions use VOH = 1.6V and VOL = 1.4V. 10. At any given temperature and voltage condition for any given device, tHZCE is less than tLZCE and tHZOE is less than tLZOE. 11. tLZCE, tLZWE, tHZOE, tLZOE, tHZCE, and tHZWE are tested with CL = 5pF as in (b) of AC Test Loads and Waveforms. Transition is measured 500 mV from steady state voltage.
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CY7C132, CY7C136 CY7C136A, CY7C142, CY7C146
Switching Characteristics
Over the Operating Range (Speeds -15, -25, -30) [8] (continued) 7C136-15 [4] 7C146-15 Min Write tWC tSCE tAW tHA tSA tPWE tSD tHD tHZWE tLZWE tBLA tBHA tBLC tBHC tPS tWB tWH tBDD tDDD tWDD tWINS tEINS tINS tOINR tEINR tINR Cycle[12] Write Cycle Time CE LOW to Write End Address Setup to Write End Address Hold from Write End Address Setup to Write Start R/W Pulse Width Data Setup to Write End Data Hold from Write End R/W LOW to High Z
[7]
Parameter
Description
7C132-25 [4] 7C136-25 7C142-25 7C146-25 Min 25 20 20 2 0 15 15 0 Max
7C132-30 7C136-30 7C142-30 7C146-30 Min 30 25 25 2 0 25 15 0 Max
Unit
Max
15 12 12 2 0 12 10 0 10 0 15 15 15 15 5 0 13 15 Note 15 Note 15 15 15 15 15 15 15
ns ns ns ns ns ns ns ns 15 ns ns 20 20 20 20 ns ns ns ns ns ns ns 30 Note 15 Note 15 25 25 25 25 25 25 ns ns ns ns ns ns ns ns ns
15 0 20 20 20 20 5 0 20 25 Note 15 Note 15 25 25 25 25 25 25 5 0 30 0
R/W HIGH to Low Z [7] BUSY LOW from Address Match BUSY HIGH from Address BUSY LOW from CE LOW BUSY HIGH from CE HIGH[13] Port Set Up for Priority R/W LOW after BUSY LOW[14] R/W HIGH after BUSY HIGH BUSY HIGH to Valid Data Write Data Valid to Read Data Valid Write Pulse to Data Delay
[16]
Busy/Interrupt Timing Mismatch[13]
Interrupt Timing
R/W to INTERRUPT Set Time CE to INTERRUPT Set Time Address to INTERRUPT Set Time OE to INTERRUPT Reset Time[13] CE to INTERRUPT Reset Time
[13]
Address to INTERRUPT Reset Time[13]
Shaded areas contain preliminary information. Notes 12. The internal write time of the memory is defined by the overlap of CE LOW and R/W LOW. Both signals must be LOW to initiate a write and either signal can terminate a write by going HIGH. The data input setup and hold timing must be referenced to the rising edge of the signal that terminates the write. 13. These parameters are measured from the input signal changing, until the output pin goes to a high impedance state. 14. CY7C142/CY7C146 only. 15. A write operation on Port A, where Port A has priority, leaves the data on Port B's outputs undisturbed until one access time after one of the following: BUSY on Port B goes HIGH. Port B's address toggled. CE for Port B is toggled. R/W for Port B is toggled during valid read. 16. 52-pin PLCC and PQFP versions only.
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CY7C132, CY7C136 CY7C136A, CY7C142, CY7C146
Switching Characteristics
Over the Operating Range (Speeds -35, -45, -55) [8] 7C132-35 7C136-35 7C142-35 7C146-35 Min Read Cycle tRC tAA tOHA tACE tDOE tLZOE tHZOE tLZCE tHZCE tPU tPD Write tWC tSCE tAW tHA tSA tPWE tSD tHD tHZWE tLZWE tBLA tBHA tBLC tBHC tPS tWB tWH tBDD tDDD tWDD Cycle[12] Write Cycle Time CE LOW to Write End Address Setup to Write End Address Hold from Write End Address Setup to Write Start R/W Pulse Width Data Setup to Write End Data Hold from Write End R/W LOW to High Z [7] R/W HIGH to Low Z [7] BUSY LOW from Address Match BUSY HIGH from Address BUSY LOW from CE LOW BUSY HIGH from CE HIGH[13] 5 0 30 35 Note 15 Note 15 Port Set Up for Priority R/W LOW after BUSY LOW[14] R/W HIGH after BUSY HIGH BUSY HIGH to Valid Data Write Data Valid to Read Data Valid Write Pulse to Data Delay Mismatch[13] 0 20 20 20 20 5 0 35 45 Note 15 Note 15 35 30 30 2 0 25 15 0 20 0 25 25 25 25 5 0 35 45 Note 15 Note 15 45 35 35 2 0 30 20 0 20 0 30 30 30 30 55 40 40 2 0 30 20 0 25 ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns Read Cycle Time Address to Data Valid[9] Data Hold from Address Change CE LOW to Data Valid OE LOW to Low
[9]
Parameter
Description
7C132-45 7C136-45 7C142-45 7C146-45 Min 45 Max
7C132-55 7C136-55 7C136A-55 7C142-55 7C146-55 Min 55 Max
Unit
Max
35 35 0 35 20 3 20 5 20 0 35
ns 55 ns ns 55 25 ns ns ns 25 ns ns 25 ns ns 35 ns
45 0 45 25 3 20 5 20 0 35 0 5 3 0
OE LOW to Data Valid[9] Z[7, 10] OE HIGH to High Z[7, 10, 11] CE LOW to Low Z[7, 10] CE HIGH to High Z[7, 10, 11] Down[7] CE LOW to Power Up[7] CE HIGH to Power
Busy/Interrupt Timing
Document #: 38-06031 Rev. *E
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CY7C132, CY7C136 CY7C136A, CY7C142, CY7C146
Switching Characteristics
Over the Operating Range (Speeds -35, -45, -55) [8] (continued) 7C132-35 7C136-35 7C142-35 7C146-35 Min Interrupt tWINS tEINS tINS tOINR tEINR tINR Timing [16] R/W to INTERRUPT Set Time CE to INTERRUPT Set Time Address to INTERRUPT Set Time OE to INTERRUPT Reset Time[13] Time[13] CE to INTERRUPT Reset Time[13] Address to INTERRUPT Reset 25 25 25 25 25 25 35 35 35 35 35 35 45 45 45 45 45 45 ns ns ns ns ns ns Max 7C132-45 7C136-45 7C142-45 7C146-45 Min Max 7C132-55 7C136-55 7C136A-55 7C142-55 7C146-55 Min Max
Parameter
Description
Unit
Switching Waveforms
Figure 4. Read Cycle No. 1 (Either Port-Address Access) [17, 18]
tRC ADDRESS tOHA DATA OUT PREVIOUS DATA VALID tAA DATA VALID
Figure 5. Read Cycle No. 2 (Either Port-CE/OE )[17, 19]
CE OE tACE tDOE tHZOE tHZCE
tLZOE tLZCE DATA OUT tPU ICC ISB
DATA VALID tPD
Notes 17. R/W is HIGH for read cycle. 18. Device is continuously selected, CE = VIL and OE = VIL. 19. Address valid prior to or coincident with CE transition LOW.
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CY7C132, CY7C136 CY7C136A, CY7C142, CY7C146
Switching Waveforms
(continued)
Figure 6. Read Cycle No. 3 (Read with BUSY Master: CY7C132 and CY7C136/CY7C136A)
tRC ADDRESSR R/WR DINR tPS ADDRESSL BUSYL tBLA DOUTL tWDD tDDD ADDRESS MATCH tBHA tBDD VALID ADDRESS MATCH tPWE
VALID
Figure 7. Write Cycle No.1 (OE Three-States Data I/Os--Either Port) [12, 20]
tWC ADDRESS tSCE CE tSA R/W tSD DATAIN DATA VALID tHD tAW tHA tPWE
OE tHZOE HIGH IMPEDANCE DOUT
Note 20. If OE is LOW during a R/W controlled write cycle, the write pulse width must be the larger of tPWE or tHZWE + tSD to allow the data I/O pins to enter high impedance and for data to be placed on the bus for the required tSD.
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CY7C132, CY7C136 CY7C136A, CY7C142, CY7C146
Switching Waveforms
(continued)
Figure 8. Write Cycle No. 2 (R/W Three-States Data I/Os--Either Port)[12, 21]
tWC ADDRESS tSCE CE tSA R/W tSD DATAIN tHZWE DOUT tHD tAW tPWE tHA
DATA VALID tLZWE HIGH IMPEDANCE
Figure 9. Busy Timing Diagram No. 1 (CE Arbitration) CEL Valid First:
ADDRESSL,R CEL tPS CER tBLC BUSYR tBHC ADDRESS MATCH
CER Valid First:
ADDRESSL,R CER tPS CEL tBLC BUSYL tBHC
ADDRESS MATCH
Note 21. If the CE LOW transition occurs simultaneously with or after the R/W LOW transition, the outputs remain in a high impedance state.
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CY7C132, CY7C136 CY7C136A, CY7C142, CY7C146
Switching Waveforms
Left Address Valid First:
tRC or tWC ADDRESSL ADDRESS MATCH tPS ADDRESSR tBLA BUSYR tBHA ADDRESS MISMATCH
(continued) Figure 10. Busy Timing Diagram No. 2 (Address Arbitration)
Right Address Valid First:
tRC or tWC ADDRESSR ADDRESS MATCH tPS ADDRESSL tBLA BUSYL tBHA ADDRESS MISMATCH
Figure 11. Busy Timing Diagram No. 3 (Write with BUSY, Slave: CY7C142/CY7C146)
CE
tPWE R/W tWB BUSY tWH
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CY7C132, CY7C136 CY7C136A, CY7C142, CY7C146
Switching Waveforms
(continued)
Interrupt Timing Diagrams [16]
Figure 12. Left Side Sets INTR
tWC ADDRESSL CEL R/WL tSA INTR tINS WRITE 7FF tHA
tEINS
tWINS
Figure 13. Right Side Clears INTR
tRC ADDRESSR tHA CER tEINR R/WR READ 7FF tINR
OER tOINR INTR
Figure 14. Right Side Sets INTL
tWC ADDRESSR tINS CER tEINS R/WR INTL tSA tWINS WRITE 7FE tHA
Figure 15. Right Side Clears INTL
tRC ADDRESSL CEL tEINR R/WL OEL tOINR INTL tHA READ 7FE tINR
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CY7C132, CY7C136 CY7C136A, CY7C142, CY7C146
Figure 16. Typical DC and AC Characteristics
OUTPUT SOURCE CURRENT (mA)
NORMALIZED SUPPLY CURRENT vs. SUPPLY VOLTAGE 1.4 1.2 NORMALIZED SUPPLY CURRENT vs. AMBIENT TEMPERATURE OUTPUT SOURCE CURRENT vs. OUTPUT VOLTAGE 120 100 80 60 40 20 0 0 1.0 2.0 3.0 4.0 OUTPUT VOLTAGE (V) OUTPUT SINK CURRENT vs. OUTPUT VOLTAGE 140 120 100 80 60 40 20 0 0.0 1.0 VCC = 5.0V TA = 25C 2.0 3.0 4.0 VCC = 5.0V TA = 25C
NORMALIZED ICC, ISB
1.2 1.0 0.8 0.6 0.4 0.2 0.0 4.0 4.5
NORMALIZED ICC, ISB
ICC
1.0 0.8 0.6 0.4 0.2
ICC
VCC = 5.0V VIN = 5.0V
ISB3 5.0 5.5 6.0
ISB3 25 125
0.6 -55
SUPPLY VOLTAGE (V) NORMALIZED ACCESS TIME vs. SUPPLY VOLTAGE 1.4 1.6
AMBIENT TEMPERATURE (C) NORMALIZED ACCESS TIME vs. AMBIENT TEMPERATURE
NORMALIZED tAA
NORMALIZED tAA
1.3 1.2 1.1 1.0 0.9 0.8 4.0 4.5 5.0 5.5 6.0 TA = 25C
1.4 1.2 1.0 VCC = 5.0V 0.8 0.6 -55
25
125
SUPPLY VOLTAGE (V) TYPICAL POWER-ON CURRENT vs. SUPPLY VOLTAGE 3.0 30.0 25.0
AMBIENT TEMPERATURE (C) TYPICAL ACCESS TIME CHANGE vs. OUTPUT LOADING 1.25
OUTPUT SINK CURRENT (mA)
OUTPUT VOLTAGE (V) NORMALIZED ICC vs. CYCLE TIME VCC = 5.0V TA = 25C VIN = 0.5V 1.0
NORMALIZED tPC
2.0 1.5 1.0 0.5 0.0 0 1.0 2.0 3.0 4.0 5.0
20.0 15.0 10.0 5.0 0 0 200 400 VCC = 4.5V TA = 25C 600 800 1000
NORMALIZED ICC
2.5
DELTA tAA (ns)
0.75
0.50 10
20
30
40
SUPPLY VOLTAGE (V)
CAPACITANCE (pF)
CYCLE FREQUENCY (MHz)
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CY7C132, CY7C136 CY7C136A, CY7C142, CY7C146
Ordering Information
Speed (ns) 15 25 Ordering Code CY7C136-15JC CY7C136-15NC CY7C136-25JC CY7C136-25JXC CY7C136-25NC CY7C136-25NXC CY7C136-25JXI 30 CY7C136-30JC CY7C136-30NC CY7C136-30JI 35 CY7C136-35JC CY7C136-35NC CY7C136-35JI 45 CY7C136-45JC CY7C136-45NC CY7C136-45JI 55 CY7C136-55JC CY7C136-55JXC CY7C136-55NC CY7C136-55NXC CY7C136-55JI CY7C136A-55JXI CY7C136-55NI CY7C136A-55NXI 15 25 CY7C146-15JC CY7C146-15NC CY7C146-25JC CY7C146-25JXC CY7C146-25NC 30 CY7C146-30JC CY7C146-30NC CY7C146-30JI 35 CY7C146-35JC CY7C146-35NC CY7C146-35JI 45 CY7C146-45JC CY7C146-45NC CY7C146-45JI 55 CY7C146-55JC CY7C146-55JXC CY7C146-55NC CY7C146-55JI 51-85042 51-85004 51-85042 51-85004 51-85042 51-85004 51-85004 51-85042 51-85004 51-85004 51-85042 51-85004 51-85004 51-85004 51-85042 51-85004 51-85042 51-85004 51-85042 51-85004 51-85004 51-85042 51-85004 51-85004 51-85042 51-85004 51-85004 51-85042 51-85004 51-85004 51-85042 Package Diagram 51-85004 51-85042 51-85004 Package Type 52-Pin Plastic Leaded Chip Carrier 52-Pin Plastic Quad Flatpack 52-Pin Plastic Leaded Chip Carrier 52-Pin Plastic Leaded Chip Carrier (Pb-Free) 52-Pin Plastic Quad Flatpack 52-Pin Plastic Quad Flatpack (Pb-Free) 52-Pin Plastic Leaded Chip Carrier (Pb-Free) 52-Pin Plastic Leaded Chip Carrier 52-Pin Plastic Quad Flatpack 52-Pin Plastic Leaded Chip Carrier 52-Pin Plastic Leaded Chip Carrier 52-Pin Plastic Quad Flatpack 52-Pin Plastic Leaded Chip Carrier 52-Pin Plastic Leaded Chip Carrier 52-Pin Plastic Quad Flatpack 52-Pin Plastic Leaded Chip Carrier 52-Pin Plastic Leaded Chip Carrier 52-Pin Plastic Leaded Chip Carrier (Pb-Free) 52-Pin Plastic Quad Flatpack 52-Pin Plastic Quad Flatpack (Pb-Free) 52-Pin Plastic Leaded Chip Carrier 52-Pin Plastic Leaded Chip Carrier (Pb-Free) 52-Pin Plastic Quad Flatpack 52-Pin Plastic Quad Flatpack (Pb-Free) 52-Pin Plastic Leaded Chip Carrier 52-Pin Plastic Quad Flatpack 52-Pin Plastic Leaded Chip Carrier 52-Pin Plastic Leaded Chip Carrier (Pb-Free) 52-Pin Plastic Quad Flatpack 52-Pin Plastic Leaded Chip Carrier 52-Pin Plastic Quad Flatpack 52-Pin Plastic Leaded Chip Carrier 52-Pin Plastic Leaded Chip Carrier 52-Pin Plastic Quad Flatpack 52-Pin Plastic Leaded Chip Carrier 52-Pin Plastic Leaded Chip Carrier 52-Pin Plastic Quad Flatpack 52-Pin Plastic Leaded Chip Carrier 52-Pin Plastic Leaded Chip Carrier 52-Pin Plastic Leaded Chip Carrier (Pb-Free) 52-Pin Plastic Quad Flatpack 52-Pin Plastic Leaded Chip Carrier Industrial Industrial Commercial Industrial Commercial Industrial Commercial Commercial Commercial Commercial Industrial Industrial Commercial Industrial Commercial Industrial Commercial Industrial Commercial Commercial Operating Range Commercial
Document #: 38-06031 Rev. *E
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CY7C132, CY7C136 CY7C136A, CY7C142, CY7C146
Package Diagrams
Figure 17. 52-Pin Plastic Leaded Chip Carrier, 51-85004
51-85004-*A
Figure 18. 52-Pin Plastic Quad Flatpack, 51-85042
51-85042-**
Document #: 38-06031 Rev. *E
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CY7C132, CY7C136 CY7C136A, CY7C142, CY7C146
Document History Page
Document Title: CY7C132, CY7C136, CY7C136A, CY7C142, CY7C146 2K x 8 Dual-Port Static RAM Document Number: 38-06031 Revision ** *A *B *C ECN 110171 128959 236748 393184 Submission Date 10/21/01 09/03/03 See ECN See ECN Orig. of Change SZV JFU YDT YIM Description of Change Change from Spec number: 38-06031 Added CY7C136-55NI to Order Information Removed cross information from features section Added Pb-Free Logo Added Pb-Free parts to ordering information: CY7C136-25JXC, CY7C136-25NXC, CY7C136-55JXC, CY7C136-55NXC, CY7C136-55JXI, CY7C136-55NXI, CY7C146-25JXC, CY7C146-55JXC
*D
2623658
12/17/08
VKN/PYRS Added CY7C136-25JXI part Removed CY7C132/142 from the Ordering information table Removed 48-Pin DIP and 52-Pin Square LCC package from the data sheet
*E
2678221
03/24/2009 VKN/AESA Added CY7C136A-55JXI, and CY7C136A-55NXI parts.
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(c) Cypress Semiconductor Corporation, 2005-2009. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges. Any Source Code (software and/or firmware) is owned by Cypress Semiconductor Corporation (Cypress) and is protected by and subject to worldwide patent protection (United States and foreign), United States copyright laws and international treaty provisions. Cypress hereby grants to licensee a personal, non-exclusive, non-transferable license to copy, use, modify, create derivative works of, and compile the Cypress Source Code and derivative works for the sole purpose of creating custom software and or firmware in support of licensee product to be used only in conjunction with a Cypress integrated circuit as specified in the applicable agreement. Any reproduction, modification, translation, compilation, or representation of this Source Code except as specified above is prohibited without the express written permission of Cypress. Disclaimer: CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS MATERIAL, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. Cypress reserves the right to make changes without further notice to the materials described herein. Cypress does not assume any liability arising out of the application or use of any product or circuit described herein. Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress' product in a life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges. Use may be limited by and subject to the applicable Cypress software license agreement.
Document #: 38-06031 Rev. *E
Revised March 24, 2009
Page 15 of 15
All products and company names mentioned in this document may be the trademarks of their respective holders.
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